1. Field of the Invention
The present invention relates to a phase-locked loop (PLL) circuit, and more particularly, to a dual-loop PLL circuit with offset currents.
2. Descriptions of the Related Art
Over recent years, in place of conventional single-loop designs, the dual-loop design is adopted in most phase-locked loop (PLL) circuits to reduce the area occupied by capacitors (the loop components of the PLL circuits). However, PLL circuits of the dual-loop design still have a problem in which charge pumps (CPs) thereof cannot effectively operate within a desired linear working range and consequently cause a spurious tone. On the other hand, control voltages that are outputted by the loops to a voltage control oscillator (VCO) vary significantly and continuously as the PLL circuits operate, so the VCO cannot effectively keep operating within the working range which is more linear than other ranges.
In view of the above, it is important to provide a solution in the PLL circuits of the dual-loop design that can effectively make the CPs operate within a desired linear working range and that can further control the control voltages outputted to the VCO so that the VCO can also keep operating within a desired linear working range.